1. Field of the Invention
The present invention relates, in general, to a method for the fabrication of a DRAM cell and, more particularly, to a capacitor useful for ultra large scale integration devices of 64M DRAM or larger.
2. Description of the Prior Art
The high integration of memory devices is accompanied by a great decrease in the area occupied by unit cells, making it difficult to secure the capacitance necessary to operate the memory devices. In addition, the higher the integration is, the larger the capacitance must be. Many attempts have been made to augment the capacitance in response to the securing of sufficient capacitance in such reduced area. For example, various three dimensional structures of a capacitor, such as stack, cylinder, fin and so on, have been adopted.
A significant disadvantage of the conventional techniques is that too many process steps must be undertaken to increase the capacitance, along with poor topology of the resulting capacitor.